Challenge: Dense layout; some nets hard to reach. EEPROM required to have serial number and data programed. RTC required to be programmed. FPGA required to be programmed

Solution: ICT for structural coverage; functional checks with custom I/O. Custom code to program EEPROM and RTC. Integrated device programmer for FPGA programming.

Outcome: Full coverage achieved without slowing the line.

What helped: Mixing methods to cover every risk.